1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor chip passivation structures and methods of making the same.
2. Description of the Related Art
A conventional semiconductor chip destined for flip-chip mounting to a printed circuit board or semiconductor package substrate will typically consist of two principle sides: one side provided with a plurality of input/output conductors, and an opposite side that may or may not be fitted with a heat spreader. This general configuration holds true whether the chip is implemented as a bulk silicon or semiconductor device or a semiconductor-on-insulator device. The principle side of the semiconductor chip that is provided with the input/output conductor pads typically includes one or more metallization layers that are formed above the active device portion of the chip and an array of conductor pads connected to the metallization layers by vias. The top-most metallization layer includes the array of conductor pads and is sometimes referred to as a redistribution layer. The conductors pads are provided with under bump metallization (UBM) structures suitable to provide metal diffusion resistant surfaces for solder bump placement.
In a C4 flip-chip interconnect process, a plurality of solder bumps are applied to the bump pads and a corresponding plurality of solder bumps are formed on respective conductor pads on a package substrate or printed circuit board. The respective collections of bumps are brought together and a reflow process is performed in order to establish a plurality of solder joints between the semiconductor chip and the printed circuit board or package substrate. It is important to protect the top-most metallization layer from contamination and physical damage prior to bumping and assembly with a substrate. A damaged or contaminated bump pad might lead to device failure. In a conventional process, this protective function is provided by a passivation structure that is applied to the side of the semiconductor chip that includes the bump pads. The passivation structure undergoes a masking and etch process to expose the conductor pads. A polyimide layer is often applied over the passivation layer, including over the previously etched openings to the conductor pads, to provide protection from thermomechanical stresses that might otherwise damage chip structures. Thereafter, the polyimide layer is lithographically processed to essentially reestablish openings leading to the underlying bump pads, and then metal deposition processes and solder application processes are used in order to establish the under bump metallization and solder bumps.
In one conventional process, a passivation structure consists of a six layer stack of alternating layers of silicon nitride and undoped silicate glass. Processing at this stage is done at the wafer level, so application of each of the silicon nitride and undoped silicate glass layers requires the wafer to be moved in and out of a chemical vapor deposition (CVD) chamber and subjected to CVD in order to establish a given layer. Consequently, a dozen or more material movements and steps will be required in order to establish a conventional six layer passivation stack as well as the six deposition processes themselves. The number of both material handling and CVD processes represents an investment of manufacturing time and materials.
In some conventional processes, the steps of passivation structure formation and polyimide layer application are divided between different, and often geographically separated, manufacturing facilities. For example, it is not uncommon for one vendor to manufacture the semiconductor chip up to and including the passivation structure. At this point, the wafer is shipped to a bumping vendor that applies the polyimide layer and then performs the subsequent lithographic processing to form the UBM structures and solder bumps. Thus, the passivation structure is formed by one vendor and the polyimide and under bump metallization are formed subsequently by another vendor.
The present invention is directed to improving upon the aforementioned conventional techniques.